Department of Electrical, Electronic, and Communication Engineering,
 Faculty of Science and Engineering, Chuo University
 Graduate School of Science and Engineering, Chuo University

Publications
International Conference Journal Book United States Patents
Japanese Patents European Patents German Patents Korean Patents
Taiwan Patents Domestic Conference Review Media
Journal
Tomoya Ishii, Sheyang Ning, Masahiro Tanaka, Kota Tsurumi and Ken Takeuchi, “Adaptive Comparator Bias-Current Control of 0.6 V Input Boost Converter for ReRAM Program Voltages in Low Power Embedded Applications,” IEEE J. of Solid-State Circuits, vol. 51, no. 10, pp. 2389-2397 , October 2016.
Sheyang Ning, Tomoko Ogura Iwasaki, Shuhei Tanakamaru, Darlene Viviani, Henry Huang, Monte Manning, Thomas Rueckes and Ken Takeuchi, “Reset-Check-Reverse-Flag Scheme on NRAM with 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory,” IEEE J. of Solid-State Circuits, vol. 51, no. 8, pp. 1938-1951, August 2016.
Masafumi Doi, Tsukasa Tokutomi, Shogo Hachiya, Atsuro Kobayashi, Shuhei Tanakamaru, Sheyang Ning, Tomoko Ogura Iwasaki and Ken Takeuchi, “Quick-Low-Density Parity Check (LDPC) and Dynamic Threshold Voltage (VTH) Optimization in 1Xnm Triple-Level Cell (TLC) NAND Flash Memory with Comprehensive Analysis of Endurance, Retention-Time and Temperature Variation,” Japanese Journal of Applied Physics (JJAP), vol. 55, no. 8, 084201, July 2016.
Senju Yamazaki, Tomoko Ogura Iwasaki, Shogo Hachiya, Tomonori Takahashi and Ken Takeuchi, “A 72% Error Reduction Scheme Based on Temperature Acceleration for Long-Term Data Storage Applications: Cold Flash and Millennium Memories,” Solid-State Electronics, vol. 121, pp.25-33, July 2016.
Shuhei Tanakamaru, Shogo Hosaka, Koh Johguchi, Hirofumi Takishita and Ken Takeuchi, “Understanding Relation Between Performance and Reliability of NAND Flash / SCM Hybrid Solid-State Drive (SSD),” IEEE Transactions on VLSI Systems, vol. 24, no. 6, pp. 2208 - 2219, June 2016.
Hirofumi Takishita, Shuhei Tanakamaru, Sheyang Ning and Ken Takeuchi, “Trade-off of Performance, Reliability and Cost of SCM/NAND Flash Hybrid SSD,” IEICE Transactions on Electronics, E99-C, vol. 4, pp. 444-451, April 2016 .
Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda and Ken Takeuchi, “An Inductively-Powered Wireless Solid-State Drive System with Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories,” IEEE J. of Solid-State Circuits, vol. 51, no. 4, pp. 1041-1050, April 2016.
Masahiro Tanaka, Shogo Hachiya, Tomoya Ishii, Sheyang Ning, Kota Tsurumi and Ken Takeuchi, “0.6-1.0 V Operation Set/Reset Voltage (3V) Generator for 3D-integrated ReRAM and NAND flash Hybrid Solid-State Drive,” Japanese Journal of Applied Physics (JJAP), vol. 55, no. 4S, 04EE07, March 2016.
Ken Takeuchi, “Memory System Architecture for the Data Centric Computing,” Japanese Journal of Applied Physics (JJAP), vol. 55, no. 4S, 04EA02, February 2016.
Sheyang Ning, Tomoko Ogura Iwasaki, Shogo Hachiya, Glen Rosendale, Monte Manning, Darlene Viviani, Thomas Rueckes and Ken Takeuchi, “Carbon Nanotube Memory Cell Array Program Error Analysis and Tradeoff between Reset Voltage and Verify Pulses,” Japanese Journal of Applied Physics (JJAP), vol. 55, no. 4S, 04EE01, February 2016.
Tomoko Ogura Iwasaki, Sheyang Ning, Hiroki Yamazawa and Ken Takeuchi, “Array-level Stability Enhancement of 50nm AlxOy ReRAM,” Solid-State Electronics, vol. 114, pp. 1-8, December 2015.
Sheyang Ning, Tomoko Ogura Iwasaki, Kazuya Shimomura, Koh Johguchi, Eisuke Yanagizawa, Glen Rosendale, Monte Manning, Darlene Viviani, Thomas Rueckes and Ken Takeuchi, “Investigation and Improvement of Verify-program in Carbon Nanotube Based Non-volatile Memory,” IEEE Transactions on Electron Devices, vol. 62, no. 9, pp. 2837-2844, September 2015.
Tsukasa Tokutomi, Shuhei Tanakamaru, Tomoko Ogura Iwasaki and Ken Takeuchi, “Advanced Error-Prediction LDPC with temperature compensation for Highly Reliable SSDs,” Solid-State Electronics, vol. 111, pp. 129-140, September 2015.
Takahiro Onagi, Chao Sun and Ken Takeuchi, “Design Guidelines of Storage Class Memory Based Solid-State Drives to Balance Performance, Power, Endurance and Cost,” Japanese Journal of Applied Physics (JJAP), vol. 54, no. 4S, 04DE04, April 2015.
Shuhei Tanakamaru, Hiroki Yamazawa, Tsukasa Tokutomi, Sheyang Ning and Ken Takeuchi, “Design Methodology for Highly Reliable, High Performance ReRAM and 3-bit/cell MLC NAND Flash Solid-State Storage,” IEEE Transactions on Circuits and Systems I, vol. 62, no. 3, pp. 844-853, March 2015.
Shuhei Tanakamaru, Yuta Kitamura, Senju Yamazaki, Tsukasa Tokutomi and Ken Takeuchi, “Highly Reliable Coding Methods for Emerging Applications: Archive and Enterprise Solid-State Drives (SSDs),” IEEE Transactions on Circuits and Systems I, vol. 62, no. 3, pp. 771-780, March 2015.
Teruyoshi Hatanaka, Koh Johguchi and Ken Takeuchi, “Experimental investigation of program-voltage (20 V) generation with boost converter for 3D-stacked NAND Flash SSD,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 5, no. 2, pp. 188-193, February 2015.
Chao Sun, Ayumi Soga, Chihiro Matsui, Asuka Arakawa and Ken Takeuchi, “LBA Scrambler: A NAND Flash Aware Data Management Scheme for High-Performance Solid-State Drives,” IEEE Transactions on VLSI Systems, vol. 24, no. 1, pp. 115-128, January 2015.
Shuhei Tanakamaru, Masafumi Doi and Ken Takeuchi, “A Design Strategy of Error-Prediction Low-Density Parity-Check (EP-LDPC) Error-Correcting Code (ECC) and Error-Recovery Schemes for Scaled NAND Flash Memories,” IEICE Transactions on Electronics, E98-C, vol. 1, pp. 53-61, January 2015.
Sheyang Ning, Tomoko Ogura Iwasaki and Ken Takeuchi, “50 nm AlxOy ReRAM program 31% energy, 1.6× endurance, and 3.6× speed improvement by advanced cell condition adaptive verify-reset,” Solid-State Electronics, vol. 103, pp. 64-72, January 2015.
Chao Sun, Asuka Arakawa and Ken Takeuchi, “SEA-SSD: A Storage Engine Assisted SSD with Application-Coupled Simulation Platform,” IEEE Transactions on Circuits and Systems I, vol. 62, no. 1, pp. 120-129, January 2015.
Chao Sun, Tomoko Ogura Iwasaki, Takahiro Onagi, Koh Johguchi and Ken Takeuchi, “Cost, Capacity and Performance Analyses for Hybrid SCM/NAND Flash SSD,” IEEE Transactions on Circuits and Systems I, vol. 61, no. 8, pp. 2360 - 2369, August 2014.
Koh Johguchi, Kasuaki Yoshioka and Ken Takeuchi, “NAND Phase Change Memory with Block-Erase Architecture and Pass-Transistor Design Requirements for Write and Disturbance,” IEICE Transactions on Electronics, E97-C, no. 4, pp. 351-359, April 2014.
Koh Johguchi, Toru Egami, Kousuke Miyaji and Ken Takeuchi, “A Temperature Tracking Read Reference Current and Write Voltage Generator for Multi-Level Phase Change Memories,” IEICE Transactions on Electronics, E97-C, no. 4, pp. 342-350, April 2014.
Masafumi Doi, Shuhei Tanakamaru and Ken Takeuchi, “A Scaling Scenario of Asymmetric Coding to reduce both Data Retention and Program Disturbance of NAND Flash Memories,” Solid-State Electronics, vol. 92, pp. 63-69, April 2014.
Toru Egami, Koh Johguchi, Senju Yamazaki and Ken Takeuchi,  “Investigation of Multi-Level-Cell and SET Operations on Super-Lattice Phase Change Memories,” Japanese Journal of Applied Physics (JJAP), vol. 53, 04ED02, April 2014.
Sheyang Ning, Tomoko Ogura Iwasaki and Ken Takeuchi,  “50nm AlxOy ReRAM Array Program Bit Error Reduction and High Temperature Operation,” Japanese Journal of Applied Physics (JJAP), vol. 53, 04ED09, April 2014.
Shogo Hachiya, Koh Johguchi, Kousuke Miyaji and Ken Takeuchi,  “Hybrid Triple-Level-Cell (TLC) /Multi-Level-Cell (MLC) NAND Flash Storage Array with Chip Exchangeable Method,” Japanese Journal of Applied Physics (JJAP), vol. 53, 04EE04, April 2014.
Kousuke Miyaji, Chao Sun, Ayumi Soga and Ken Takeuchi,  “Co-Design of Application Software and NAND Flash Memory in Solid-State Drive for Relational Database Storage System,” Japanese Journal of Applied Physics (JJAP), vol. 53, 04EE09, April 2014.
Shuhei Tanakamaru, Masafumi Doi and Ken Takeuchi, “NAND Flash Memory / ReRAM Hybrid Unified Solid-State-Storage Architecture,” IEEE Transactions on Circuits and Systems I, vol. 61, no. 4, pp. 1119-1132, April 2014.
Kousuke Miyaji, Yuki Yanagihara, Reo Hirasawa, Sheyang Ning and Ken Takeuchi,  “Control Gate Length, Spacing, Channel Hole Diameter and Stacked Layer Number Design for BiCS-Type 3D-Stackable NAND Flash Memory,” Japanese Journal of Applied Physics (JJAP), vol. 53, 024201, January 2014.
Kazuhide Higuchi, Tomoko Ogura Iwasaki and Ken Takeuchi, “Evaluation of Voltage vs. Pulse Width Modulation and Feedback during Set/Reset Verify-Programming to Achieve 10 Million Cycles for 50nm HfO2 ReRAM,” Solid-State Electronics, vol. 91, pp. 67-73, January 2014.
Ken Takeuchi, “NAND Flash Application and Solution,” IEEE Solid-State Circuits Magazine, vol. 5, no. 4, pp. 34-40, December, 2013.
Shuhei Tanakamaru, Yuki Yanagihara and Ken Takeuchi, “Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs),” IEEE J. of Solid-State Circuits, vol. 48, no. 11, pp. 1-14, November, 2013.
Chao Sun, Kousuke Miyaji, Koh Johguchi and Ken Takeuchi, “A High Performance and Energy-Efficient Cold Data Eviction Algorithm for 3D-TSV Hybrid ReRAM/MLC NAND SSD,” IEEE Transactions on Circuits and Systems I, vol. 61, no. 2, pp. 382-392, February 2014.
Ken Takeuchi, “Storage Class Memory & NAND Flash Memory Hybrid Solid-State Drives (SSD)” Electrochemical Society Meeting (ECS) Transactions, vol. 58, no. 5, pp 3-8, October 2013.
Kousuke Miyaji, Toshikazu Suzuki and Ken Takeuchi, “A 6T-SRAM with a Post-Process Electron Injection Scheme that Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy,” IEEE J. of Solid-State Circuits, vol. 48, no. 9, pp. 2239-2249, September, 2013.
Tomoko Ogura Iwasaki, Sheyang Ning and Ken Takeuchi,  “Forward and Reverse Biasing in Resistive Memories for Fast, Disturb-Free Read, and Verify,” Japanese Journal of Applied Physics (JJAP), vol. 52, 04CD12, April 2013.
Koh Johguchi, Toshimichi Shintani, Takahiro Morikawa, Kazuaki Yoshioka and Ken Takeuchi, “x10 Fast Write, 80% Energy Saving Temperature Control-ling Set Method for Multi-Level Cell Phase Change Memo-ries to Solve the Scaling Blockade,” Solid-State Electronics, vol. 81, pp. 78- 85, March 2013.
Ken Takeuchi, Teruyoshi Hatanaka and Shuhei Tanakamaru,  “Highly Reliable, High Speed and Low Power NAND Flash Memory-Based Solid State Drives (SSDs),” IEICE Electronics Express (ELEX), vol. 9, no. 8, pp. 779-794, August 2012. 【招待論文】
Teruyoshi Hatanaka and Ken Takeuchi, “NAND Controller System with Channel Number Detection and Feedback for Power-Efficient High-Speed 3D-SSD,” IEEE J. of Solid-State Circuits, vol. 47, no. 6, pp. 1460-1468, June 2012.
Kousuke Miyaji, Yasuhiro Shinozuka, Shinji Miyano and Ken Takeuchi, “Near Threshold Voltage Word-line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM,” IEEE Transactions on Circuits and Systems I, vol. 59, no. 8, pp. 1635-1643, August 2012.
Xizhen Zhang, Mitsue Takahashi, Ken Takeuchi, and Shigeki Sakai,  “64 kbit Ferroelectric-Gate-Transistor-Integrated NAND Flash Memory with 7.5 V Program and Long Data Retention,” Japanese Journal of Applied Physics (JJAP), vol. 51, no. 4, pp. 04DD01, April 2012.
Koh Johguchi, Teruyoshi Hatanaka and Ken Takeuchi,  “Through-Silicon-Via (TSV) Design with Clustering Structure and Adaptive TSV Control for 3D Solid-State-Drive Boost Converter System,” Japanese Journal of Applied Physics (JJAP), vol. 51, no. 2, pp. 02BE02, February 2012.
Kousuke Miyaji, Chinglin Hung and Ken Takeuchi,  “Scaling Trends and Tradeoffs between Short Channel Effect and Channel Boosting Characteristics in sub-20nm Bulk/SOI NAND Flash Memory,” Japanese Journal of Applied Physics (JJAP), vol. 51, no. 4, pp. 04DD12, April 2012.
Kazuhide Higuchi, Kousuke Miyaji, Koh Johguchi and Ken Takeuchi,  “Endurance Enhancement and High Speed Set/Reset of 50nm Generation HfO2?based Resistive Random Access Memory (ReRAM) Cell by Intelligent Set/Reset Pulse Shape Optimization and Verify Scheme,” Japanese Journal of Applied Physics (JJAP), vol. 51, no. 2, pp. 02BD07, February 2012.
Kousuke Miyaji, Yasuhiro Shinozuka and Ken Takeuchi,  “Zero Additional Process, Local Charge Trap, Embedded Flash Memory with Drain-side Assisted Erase Scheme Using Minimum Channel Length/Width Standard CMOS Single Transistor Cell,” Japanese Journal of Applied Physics (JJAP), vol. 51, no. 4, pp. 04DD02, April 2012.
Kousuke Miyaji, Kentaro Honda, Shuhei Tanakamaru, Shinji Miyano and Ken Takeuchi, “Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor,” IEICE Transactions on Electronics, E95-C, no. 4, pp. 564-571, April 2012.
Kousuke Miyaji, Ryoji Yajima, Teruyoshi Hatanaka, Mitsue Takahashi, Shigeki Sakai and Ken Takeuchi, “Initialize & and Weak-Program Erasing Scheme and Single-Pulse Programming Scheme for High-Performance and High-Reliability Ferroelectric NAND Flash Solid-State Drive,” IEICE Transactions on Electronics, E95-C, no. 4, pp. 609-616, April 2012.
Shuhei Tanakamaru, Chinglin Hung and Ken Takeuchi, “Highly Reliable Lower Power Solid-State Drives (SSDs) Embedded with and Intelligent NAND Flash Memory Controller with Asymmetric Coding and Stripe Pattern Elimination Algorithm,” IEEE J. of Solid-State Circuits, vol. 47, no. 1, pp. 85-96, January 2012.
Shuhei Tanakamaru and Ken Takeuchi, “A 0.5V Operation VTH Loss Compensated DRAM Word-line Booster Circuit for Ultra-Low Power VLSI Systems,” IEEE J. of Solid-State Circuits, vol. 46, no. 10, pp. 2406-2415, October 2011.
Kousuke Miyaji, Shuhei Tanakamaru, Kentaro Honda, Shinji Miyano and Ken Takeuchi, “Improvement of Read Margin and its Distribution by VTH Mismatch Self-Repair in 6T-SRAM with Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection,” IEEE J. of Solid-State Circuits, vol. 46, no. 9, pp. 2180-2188, September 2011.
Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai and Ken Takeuchi, “1.8V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND,” IEEE J. of Solid-State Circuits, vol. 46, no. 6, pp. 1478-1487, June 2011.
Teruyoshi Hatanaka, Mitsue Takahashi, Shigeki Sakai and Ken Takeuchi, “Improvement of Read Disturb, Program Disturb and Data Retention by Memory Cell VTH Optimization of Ferroelectric (Fe)-NAND Flash Memories for Highly Reliable and Low Power Enterprise Solid-State Drives (SSDs),” IEICE Transactions on Electronics, vol. E94-C, no. 4, pp. 539-547, April 2011.
Mayumi Fukuda, Kazuhide Higuchi and Ken Takeuchi, “Non-volatile RAM and NAND Flash Memory-Integrated Solid-State Drives (SSDs) with Adaptive Codeword ECC for 3.6-Times Acceptable Raw Bit Error Rate Enhancement and 97% Power Reduction,” Japanese Journal of Applied Physics (JJAP), vol. 50, no.4, pp. 04DE09, April 2011.
Kousuke Miyaji, Shinji Noda, Teruyoshi Hatanaka, Mitsue Takahashi, Shigeki Sakai and Ken Takeuchi, “A 1.0V Power Supply, 9.5GByte/sec Write Speed, Single-Cell Self-Boost Program Scheme for Ferroelectric NAND Flash SSD,” Solid-State Electronics, vol. 58, no. 1, pp. 34-41, April 2011.
Shuhei Tanakamaru, Mayumi Fukuda, Kazuhide Higuchi, Atsushi Esumi, Mitsuyoshi Ito, Kai Li and Ken Takeuchi, “Post-manufacturing, 17-times Acceptable Raw Bit Error Rate Enhancement, Dynamic Codeword Transition ECC Scheme for Highly Reliable Solid-State Drives, SSDs,” Solid-State Electronics, vol. 58, no. 1, pp. 2-10, April 2011.
Koh Johguchi, Teruyoshi Hatanaka, Koichi Ishida, Tadashi Yasufuku, Makoto Takamiya, Takayasu Sakurai and Ken Takeuchi, “Through-Silicon-Via (TSV) design for a 3D-Solid-State-Drive (SSD) System with Boost Converter in a Package,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 1, no. 2, pp. 269-277, February 2011.
Shuhei Tanakamaru, Teruyoshi Hatanaka, Ryoji Yajima, Mitsue Takahashi, Shigeki Sakai and Ken Takeuchi, “A 0.5-V 6-Transistor Static Random Access Memory with Ferroelectric-Gate Field Effect Transistors,” Japanese Journal of Applied Physics (JJAP), vol. 49, no. 12, pp. 121501-121509, December 2010.
Teruyoshi Hatanaka, Ryoji Yajima, Takeshi Horiuchi, Shouyu Wang, Xizhen Zhang, Mitsue Takahashi, Shigeki Sakai and Ken Takeuchi, “Ferroelectric (Fe)-NAND Flash Memory with Batch Write Algorithm and Smart Data Store to the Non-volatile Page Buffer for Data Center Application High Speed and Highly Reliable Enterprise Solid-State Drives (SSD),” IEEE J. of Solid-State Circuits, vol. 45, no. 10, pp. 2156-2164, October 2010.
Shinji Noda, Teruyoshi Hatanaka, Kousuke Miyaji, Ryoji Yajima, Mitsue Takahashi, Shigeki Sakai and Ken Takeuchi,  “A 1.2V Power Supply, 2.43 Times Power Efficient, Adaptive Charge Pump Circuit with Optimized VTH at Each Pump Stage for Ferroelectric (Fe)-NAND Flash Memories,” Japanese Journal of Applied Physics (JJAP), vol. 49, no.4, pp. 04DD10-04DD15, April 2010.
Teruyoshi Hatanaka, Ryoji Yajima, Mitsue Takahashi, Shigeki Sakai and Ken Takeuchi,  “A Negative Word-line Voltage Negatively-Incremental Erase Pulse Scheme with ΔVTH=1/6 ΔVERASE for Enterprise Solid-State Drive (SSD) Application Ferroelectric (Fe)-NAND Flash Memories,” Japanese Journal of Applied Physics (JJAP),vol. 49, no.4, pp. 04DD08-04DD13, April 2010.
Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai and Ken Takeuchi, “Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories,” IEICE Transactions on Electronics, E93-C, no.3, pp. 317-323, March 2010.
Tsuyoshi Sekitani, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Siegfried Bauer, Ken Takeuchi, Makoto Takamiya, Takayasu Sakurai and Takao Someya, “Organic Nonvolatile Memory Transistors for Flexible Sensor Arrays,” Science, vol. 326, no. 5959, pp. 1516-1519, December 2009.
ShouyuWang, Mitue Takahashi, Qiu-Hong Li, Ken Takeuchi and Shigeki Sakai, “Operational method of a ferroelectric (Fe)-NAND flash memory array,” Semiconductor Science and Technology, 105029, 24, October 2009.
Ken Takeuchi, “Novel Co-design of NAND Flash Memory and NAND Flash Controller Circuits for sub-30nm Low-Power High-Speed Solid-State Drives (SSD),” IEEE J. of Solid-State Circuits, vol. 44, no. 4, pp. 1227-1234, April 2009.
Ken Takeuchi, Yasushi Kameda, Susumu Fujimura, Hiroyuki Otake, Koji Hosono, Hitoshi Shiga, Yoshihisa Watanabe, Takuya Futatsuyama, Yoshihiko Shindo, Masatsugu Kojima, Makoto Iwai, Masanobu Shirakawa, Masayuki Ichige, Kazuo Hatakeyama, Shinichi Tanaka, Teruhiko Kamei, Jia-Yi Fu, Adi Cernea, Yan Li, Masaaki Higashitani, Gertjan Hemink, Shinji Sato, Ken Oowada, Shih-Chung Lee, Naoki Hayashida, Jun Wan, Jeffrey Lutze, Shouchang Tsao, Mehrdad Mofidi, Kiyofumi Sakurai, Naoya Tokiwa, Hiroko Waki, Yasumitsu Nozawa, Kazuhisa Kanazawa and Shigeo Ohshima, “A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10Mbyte/sec Program Throughput,” IEEE J. of Solid-State Circuits, vol. 42, no. 1, pp. 219-232, January 2007.
Kenichi Imamiya, Hiroshi Nakamura, Toshihiko Himeno, Toshio Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Koichi Kawai, Riichiro Shirota, Norihisa Arai, Fumitaka Arai, Kazuo Hatakeyama, Hiroaki Hazama, Masanobu Saito, Hisataka Meguro, Kevin Conley, Khandker Quader and Jian J. Chen, “A 125-mm2 1-Gb NAND Flash Memory with 10MByte/sec Program Speed,” IEEE J. of Solid-State Circuits, vol. 37, no. 11, pp. 1493-1501, February 2002.
Ken Takeuchi and Tomoharu Tanaka, “A Dual Page Programming Scheme for High-Speed Multi-Gb-Scale NAND Flash Memories,” IEEE J. of Solid-State Circuits, vol. 36, no. 5, pp. 744-751, May 2001.
Ken Takeuchi, Shinji Satoh, Ken-ichi Imamiya, and Koji Sakui, “A Source-line Programming Scheme for Low Voltage Operation NAND Flash Memories,” IEEE J. of Solid-State Circuits, vol. 35, no. 5, pp. 672-681 May 2000.
Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Riichiro Shirota, Seiichi Aritome, Kazuhiro Shimizu, Kazuo Hatakeyama, and Koji Sakui, “A 130-mm2, 256-Mbit NAND Flash with Shallow Trench Isolation Technology,” IEEE J. of Solid-State Circuits, vol. 34, no. 11, pp. 1536-1542, November 1999.
Ken Takeuchi, Shinji Satoh, Tomoharu Tanaka, Ken-ichi Imamiya, and Koji Sakui, “A Negative Vth Cell Architecture for Highly Scalable, Excellently Noise-Immune, and Highly Reliable NAND Flash Memories,” IEEE J. of Solid-State Circuits, vol. 34, no. 5, pp. 675-684, June 1999.
Ken Takeuchi, Tomoharu Tanaka, and Toru Tanzawa, “A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories,” IEEE J. of Solid-State Circuits, vol. 33, no. 8, pp. 1228-1238, August 1998.
Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Riichiro Shirota, Seeichi Aritome, Hiroshi Watanabe, Gertjan Hemink, Kazuhiro Shimizu, Shinji Sato, Yuji Takeuchi, and Kazunori Ohuchi, “A Compact On-Chip ECC for Low Cost Flash Memories,” IEEE J. of Solid-State Circuits, vol. 32, no. 5, pp. 662-669, May 1997.
Ken Takeuchi, Tomoharu Tanaka, and Hiroshi Nakamura, “A Double-Level-Vth Select Gate Array Architecture for Multilevel NAND Flash Memories,” IEEE J. of Solid-State Circuits, vol. 31, no. 4, pp. 602-609, April 1996.
Ken Takeuchi, Tomoharu Tanaka, and Hiroshi Nakamura, “A Double-Level-Vth Select Gate Array Architecture for Multilevel NAND Flash Memories,” IEICE Transactions on Electronics, vol. E79-C, no. 7, pp. 1013-1020, July 1996.
Toshiharu Saiki, Ken Takeuchi, Kazuhiro Ema, Makoto Kuwata-Gonokami, K. Ohkawa, and T. Mitsuyu, “Free induction decay and quantum beat of excitons in ZnSe,” Journal of Crystal Growth, vol. 138, pp.805-808, April 1994.
Toshiharu Saiki, Ken Takeuchi, Makoto Kuwata-Gonokami, T. Mitsuyu and K. Ohkawa, “Giant excitonic optical nonlinearity in ZnSe grown by molecular beam epitaxy,” Journal of Crystal Growth, vol. 117, pp. 802-805, February 1992.
Toshiharu Saiki, Ken Takeuchi, Makoto Kuwata-Gonokami, T. Mitsuyu and K. Ohkawa, “Giant nonlinearity phase shift at exciton resonance in ZnSe,” Applied Physics Letter, vol. 60, no. 2, pp. 192-194, February 1992.

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