Department of Electrical, Electronic, and Communication Engineering,
 Faculty of Science and Engineering, Chuo University
 Graduate School of Science and Engineering, Chuo University

Publications
International Conference Journal Book United States Patents
Japanese Patents European Patents German Patents Korean Patents
Taiwan Patents Domestic Conference Review Media
 Korean Patents
Hiroshi Maejima, Katsuaki Isobe, Takumi Abe and Ken Takeuchi, "NAND flash memory device and a memory device, capable of reducing current consumption in reading data from a memory cell," K.P. 100934313B1, December 18, 2009.
Ken Takeuchi, “Semiconductor memory system capable of storing main portion of control logic on memory controller,” K.P. 100858574B1, September 8, 2008.
Ken Takeuchi and Koichi Kawai, “Semiconductor IC device to relate to electrically rewritable non-volatile semiconductor device,” K.P. 100816950B1, March 19, 2008.
Ken Takeuchi, “Semiconductor memory device using shunt line to reduce the resistance of select gate lines,” K.P. 100795646B1, January 10, 2008.
Ken Takeuchi, Takuya Futatsuyama and Koichi Kawai, “Nonvolatile memory cell having current compensated for temperature dependcency and data read method thereof,” K.P. 100790040B1, December 21, 2007.
Ken Takeuchi and Tomoharu Tanaka, “Semiconductor integrated circuit device, where thickness of gate insulation film of selection transistor is equal to thickness of gate insulation film of memory cell,” K.P. 100765011B1, October 1, 2007.
Takuya Futatsuyama and Ken Takeuchi, “Semiconductor memory device and memory card, especially suppressing coupling noise to word line when selection gate line in source side is boosted,” K.P. 100759621B1, September 11, 2007.
Takuya Futatsuyama and Ken Takeuchi, “Semiconductor memory device and memory card, especially comprising plural word Lines installed between first selection gate line and second selection gate line,” K.P. 100759615B1, September 11, 2007.
Ken Takeuchi, “Nonvolatile semiconductor memory, especially comprising mode conversion control circuit controlling conversion between high speed operation mode and low current consumption mode,” K.P. 100715412B1, April 30, 2007.
Ken Takeuchi, “Nonvolatile semiconductor memory driven at low current-compensation mode or high current-compensation mode,” K.P. 100662684B1, December 21, 2006.
Ken Takeuchi, “Threshold distribution depending on characteristics of memory cells,” K.P. 100630405B1, September 25, 2006.
Kazushige Kanda, Kenichi Imamiya, Hiroshi Nakamura, Tamio Ikehashi and Ken Takeuchi “Semiconductor device and nonvolatile semiconductor memory,” K.P. 100593771B1, June 20, 2006.
Kenichi Imamiya, Hiroshi Nakamura and Ken Takeuchi, “Semiconductor memory device,” K.P. 100538728B1, December 19, 2005.
Noboru Shibata, Ken Takeuchi and Tomoharu Tanaka, “Non-volatile semiconductor memory”, K.P. 100512501B1, August 29, 2005.
Ken Takeuchi, “Non-volatile semiconductor memory,” K.P. 100502129B1, July 8, 2005.
Tomoharu Tanaka, Koji Hosono, Tamio Ikehashi, Kenichi Imamiya, Hiroshi Nakamura and Ken Takeuchi, “Semiconductor memory,” K.P. 100483640B1, April 7, 2005.
Ken Takeuchi and Tomoharu Tanaka, “Voltage generating circuit,” K.P. 100458409B1, November 15, 2004.
Toshihiko Himeno, Tamio Ikehashi and Ken Takeuchi, “Non-volatile semiconductor memory,” K.P. 100459627B1, November 23, 2004.
Koji Hosono, Kenichi Imamiya, Hiroshi Nakamura and Ken Takeuchi, “Non-volatile semiconductor memory device,” K.R. 100458408B1, November 15, 2004.
Toshihiko Himeno, Tamio Ikehashi and Ken Takeuchi, “Semiconductor device and testing method thereof,” K.P. 100446675B1, August 23, 2004.
Koji Hosono, Yasuo Itoh and Ken Takeuchi, “Internal voltage generating circuit and a semiconductor memory for using the same, especially for using a voltage setting circuit for setting a plurality of variable potentials by using a current addition type D/A conversion circuit,” K.R. 100292565B1, March 24, 2001.

Copyright c Takeuchi Laboratory, All Rights Reserved.