Department of Electrical, Electronic, and Communication Engineering,
 Faculty of Science and Engineering, Chuo University
 Graduate School of Science and Engineering, Chuo University

Research
Next Generation Cloud IT & Database Systems for Big Data Dependable Wireless SSD System 3D-LSI Circuit Design Ultra High-Speed SSD with Storage Class Memory
3D-Storage Class Memory Device 0.5V Extremely Low Power SRAM Fe(Ferroelectric)-NAND Flash Memory Message to prospective students
Japan-originated high capacity flash memory has been creating new portable applications such as iPhone, iPad and digital still cameras. By further increasing the memory capacity by two orders of magnitudes, $10 tablets can be realized, which will enable children in world's poorest countries to access a high-level education through an wireless internet. Since Gordon Moore advocated the "Moore's law" in 1965, under which the number of transistors in a semiconductor chip doubles every 18 months, the capacity and performance of LSIs have been improving drastically by scaling transistors. However, in 2020, when the transistor size is as small as 10nm, it is predicted that the Moore's law will face a serious scaling limit because of the quantum mechanical effect and statistical fluctuations. On the other hand, as the traffic of the "big data" through an internet drastically increases, the power consumption at data centers of IT service providers such as Google and Facebook has drastically increased, which is causing serious environmental problems.
To overcome these problems, Takeuchi Lab. is developing a IT system such as the database software for big data application, computer architecture, the low-power high-capacity storage system and the semiconductor memory devices. By optimizing a wide range of research areas such as system, software, circuit and device at the same time, Takeuchi Lab. is dedicated to realize a high-speed and low power cloud IT system.
The research topics are 1) real-time database for big data application, 2) dependable wireless SSD system, 3) 3D-LSI circuit design, 4) ultra high-speed storage system with storage class memory, 5) storage class memory device such as PRAM and ReRAM, 6) 3D-vertical nano memory, 7) energy efficient voltage generator system, 9) green data center and 10) highly-reliable signal processing. As national research projects funded by the Japanese government, Takeuchi Lab. is extensively co-working with more than 20 industry partners such as Toshiba, Mitsubishi Electric, Fujitsu and NEC as well as startups such as PFI. Students are learning various aspects of technologies by working with industry experts. Our research results are widely broadcasted in the general newspapers and magazines, which will enable students to realize that our technologies are contributing the real society. Let's join us and work together to create an innovative computer system and device!
Reaserch abstructs
 Next Generation Cloud IT System and Database for Big Data
After the IT revolution in 1990's, new IT services such as Google and Amazon.com has been growing with the internet-based service business. In addition, new mobile appliances such as smart phones and tablets which can be used through the wireless internet has been created. In the near future, not only mobile handsets, various appliances such as automobiles, robots and manufacturing machines are connected each other through the internet. As a result, these machines come to transfer huge amount of data, which is called “Internet of things” (IOT).
Various real-life data such as temperature, humidity, location, motion, conditions of machines and human actions are collected with sensor network and processed in the cloud IT system. These data are called "big data". By connecting the real-life world and cyber world, the revolutionarily efficient service can be created in the electricity supply, water supply, medical, agriculture, transportation and so on. These new world where the society is tightly connected with IT is called "cyber physical space". Smart grid and Smart city are such examples. To realize the IT-based highly efficient society, Takeuchi Lab. is developing the IT network system, that is, the sensor network and the cloud IT system for the big data collection and analysis. Especially, we are working on the real-time transaction/analysis such as the database software and the SSD storage hardware. We have successfully developed a high-speed and low-power database where the database software such as the storage engine, memory management software (FTL : Flash Translation Layer) and flash memory device closely work together and the total system is optimized. By optimizing both software and hardware, a new real-time application/service such as the automatic cruise automobile transportation system with electronic vehicles, surveillance system for the security of the city and genetic analysis will be realized. These technologies are presented at SSDM 2013. This research is carried out as a part of the New Society System Development & Verification Project based on IT fusion supported by New Energy and Industrial Technology Development Organization (NEDO).
 Dependable Wireless SSD(Solid-State Drive) System
Takeuchi Lab. is working on the system especially on a low-power high-speed SSD, Solid-State Drive, system. As the capacity of NAND flash memories drastically increases, SSD that uses the NAND flash memory as a mass storage of PC and an enterprise server is attracting a lot of attention. This project develops wireless Solid-State Drives (SSD) containing tera-byte capacity NAND flash memories and their host system with 1mm distance 10-50Gbps ultra high-speed wireless communication and power transmission capabilities. The proposed wireless SSDs are dependable against various error factors such as 1) the data retention and the endurance failure of the flash memory cells, 2) human errors such as the water contact and the unexpected power outage, 3) the contact wear-out failure of the interface and 4) the ESD failure.
In this project, we developed a 76%-reduced-error Solid-State Drive (SSD) with an extended lifetime over 10 times the usually expected lifespan. This error-prediction low-density parity-check (LDPC) error correcting code (ECC) scheme achieves both high reliability as well as a 7-times faster read. A new data retention time estimation scheme has also been developed. Errors are most effectively corrected by calibrating memory data based on threshold voltage (Vth), inter-cell coupling, write/erase cycles and data retention time. The error recovery scheme is also proposed to reduce program disturb error by 76% and data retention error by 56%. These technologies were presented at ISSCC (International Solid-State Circuit Conference) 2011, 2012 and 2013. This research is carried out as a part of the fundamental technologies for dependable VLSI system project of Core Research of Evolutional Science & Technology (CREST) supported by Japan Science and Technology Agency (JST).
Dependable LSI
 3D-LSI Circuit Design
Takeuchi Lab. is developing circuit technologies of three dimensional LSIs where multiple LSIs such as micro processors, image sensors, analog circuits, DRAMs and flash memories are stacked in one package. With an intelligent mix and match, various circuits such as analog, digital and memory are best optimized. As a result, an ultra small form factor, multi-functional, high-speed and low power consumption solution is realized. As a demonstration of 3D-LSI, we successfully developed a 3D-SSD, Solid-State Drive, which contains flash memories, DRAMs and a flash memory controller with SiP.
At ISSCC 2009 and Symposium on VLSI Circuits 2011 and 2011, we presented a boost converter-based adaptive voltage generator for a 3D-SSD. Through the circuit design, chip fabrication and chip evaluation, we experimentally demonstrated that the power consumption of the NAND flash memory decreases by 70% by dynamically controlling the frequency and the duty cycle.
3D-LSI_1
3D-LSI_2
3D-LSI_3
 Ultra High-Speed SSD with Storage Class Memory
There is a growing demand for a high performance, highly reliable and low power solid-state storage system. Takeuchi Lab. is developing a storage system, especially data management software for the high speed and low power data centers to process the “big data” such as Google search engine, Facebook, Amazon.com and Twitter. A 3D through-silicon-via (TSV)-integrated SSD with hybrid memory configuration which uses storage class memories (SCMs) and NAND flash memories is a promising solution. SCM such as ReRAM, PRAM and ReRAM is fast like DRAM and high capacity like flash memories. Among various SCMs, ReRAM is the best candidate due to its high speed, low power operation and potentially high scalability.
Takeuchi Lab. developed a 3D TSV-integrated hybrid ReRAM/multi-level-cell (MLC) NAND SSDs' architecture. NAND-like interface (I/F) and sector-access overwrite policy are proposed for the ReRAM. Furthermore, intelligent data management algorithms are proposed. The proposed algorithms suppress data fragmentation and excess usage of the MLC NAND by storing hot data in the ReRAM. As a result, 11 times performance increase, 6.9 times endurance enhancement and 93% write energy reduction are achieved compared with the conventional MLC NAND SSD. 3D TSV interconnects reduce the energy consumption by 68%. The high proposed speed memory system realizes a quick data download in smart phones and low power operation of data centers. These technologies are presented at Symposium on VLSI Circuits 2012. This research is carried out as a part of Development of high-speed nonvolatile memory technology project supported by New Energy and Industrial Technology Development Organization (NEDO) .
 3D-storage class memory device
Takeuchi Lab. is developing a new storage class memory (SCM) device which operates with a new physics principle and has a new function. We are especially working on ReRAM with transition metal oxide and PRAM with phase change materials. These SCMs are ideal memories because they are fast like DRAM and high capacity like flash memories. In the existing computing system, the memory hierarchy is composed of fast SRAM whose access time is 1ns, DRAM with 10ns access time and storage such as HDD and SSD with 1-10ms access time. Such a computer architecture has not been changed in the past 20-30 years. By realizing the storage class memory, the 5-6 orders of magnitudes performance gap between DRAM and storage are resolved.
Takeuchi Lab. is developing the SCM device with vertically 3D stacked structure for the tera-bit scale mass storage applications. Already, we developed a verify-programming method for ReRAM which achieves a 50-times higher endurance and a fast set and reset. The proposed ReRAM verify-programming method uses the incremental pulse width with turnback for the reset and the incremental voltage with turnback for the set. The endurance-cycle of ReRAM increases from 48k to 2444k cycles. As for PRAM, we proposed a NAND-tyep interface for PRAM. A NAND-type interface with set erase and reset program enables 7.7-times fast write-speed and up to 70% energy reduction of PRAM.
These technologies are presented at IMW (International Memory Workshop) 2012 and 2013. These research are partially supported by Development of high-speed nonvolatile memory technology project , New Energy and Industrial Technology Development Organization (NEDO) , and Low Power Electronics Association & Project , Ultira low voltage device project for low-carbon society .
 0.5V extremely low power SRAM
To decrease the power consumption of various electronics equipments such as mobile handsets, home electric appliances, servers and network routers, the objective of this project is decreasing the power consumption of SRAM in CPUs by one-tenth. Sub-1V operation SRAMs in advanced CMOS technology are facing a critical problem caused by the degradation in read/write stability. ] One of the root causes is the conflicted requirements for read/write operations in 6T-SRAM cell. The cell current flowing in pass gate transistors should be small at read but large at write.
To overcome this problem, we developed the asymmetric transistor cell which is realized by post-process local electron injection without process and area overhead. The asymmetric transistor s formed in one of two pass gate transistors and self-repairs the read stability of the 6T-SRAM cell. The proposed cell operation is experimentally demonstrated with the 65nm and 45nm CMOS technologies.
These technologies are presented at ISSCC 2012 and Symposium on VLSI Circuits 2010. This research is carried out as a part of Extremely low power circuits and systems project (Green-IT project) supported by New Energy and Industrial Technology Development Organization (NEDO) . We are working on this project with the Semiconductor Technology Academic Research Center (STARC) and its affiliated companies such as Fujitsu Microelectronics, NEC Electronics, Panasonic, Renesas Technology, Sharp, Sony, Toshiba, Fujitsu and Hitachi. We are also working with Sakurai, Hiramoto and Takamiya laboratories at University of Tokyo and Yoshimoto and Kawaguchi laboratories at Kobe University.
 Fe(Ferroelectric)-NAND Flash Memory
Takeuchi Lab. is developing a Fe-NAND flash memory. We proposed the world's first Fe-NAND flash memory at NVSMW (Non-volatile Semiconductor Memory Workshop) in 2008. The Fe-NAND flash memory is composed of ferroelectric field-effect transistors (FeFET) whose gate dielectric consists of a ferroelectric layer, SrBiTaO and a high-K dielectric layer, HfAlO. It is difficult to scale down the conventional floating-gate (FG) NAND flash memories below 10nm due to the serious interference with neighboring cells, reduced electrons and the random telegraph noise. The charge-trap memories like MONOS have short data retention problems. Current-driven resistive switching memories such as MRAM, PRAM and ReRAM are unscalable below 10nm because of the significant IR drop of the bit-line.
On the other hand, the Fe-NAND flash memory is voltage-driven and is in principle scalable below 10nm to the crystal unit-cell size because the data is stored with an electric polarization in a ferroelectric gate insulator. The Fe-NAND flash memory can be programmed and erased as many as 100 million cycles with a low program voltage of 6V, whereas the conventional flash memory are programmed as low as ten thousand cycles and the program voltage is as high as 20V. Due to the voltage-driven, low-voltage and high-reliability operation, the Fe-NAND flash memory is expected to replace a HDD at data centers to realize an environment-friendly IT platform.
 Message to prospective students
Our education policy is to develop “T-shaped researchers.” First, we will focus on each research theme and cultivate a principal skill that describes the vertical leg of the letter, T. Next, we will explore a broad perspective, corresponding to the horizontal line of the T, by studying the wide spread of other research fields in this lab, such as systems, software, circuits, devices and physics. Takeuchi Lab. is extensively co-working with more than 20 industry partners such as Toshiba, Mitsubishi Electric, Fujitsu and NEC as well as startups such as PFI. Students are learning various aspects of technologies by working with industry experts. Students can also learn management of technology (MOT) skills such as IP strategy and marketing.

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