Department of Electrical, Electronic, and Communication Engineering,
 Faculty of Science and Engineering, Chuo University
 Graduate School of Science and Engineering, Chuo University

Professor Ken Takeuchi
 
Ken Takeuchi is currently a Professor at the Department of Electrical, Electronic, and Communication Engineering, Faculty of Science and Engineering of Chuo University. He is now working on the VLSI circuit design, signal processing and device especially on the emerging non-volatile memories, 3D-integrated SSDs, low-power 3D-LSI circuits and ultra low-voltage SRAMs for Green-IT. He received the B.S. and M.S. degrees in Applied Physics and the Ph.D. degree in Electric Engineering from the University of Tokyo in 1991, 1993 and 2006, respectively. In 2003, he also received the M.B.A. degree from Stanford University. Since he joined Toshiba in 1993, he had been leading Toshiba's NAND flash memory circuit design for fourteen years. He was an Associate Professor at the Department of Electrical Engineering and Information Systems, Graduate School of Engineering of the University of Tokyo from 2007 till 2012. In 2012, he joined Chuo University. He designed six world's highest density NAND flash memory products such as 0.7µm 16Mbit, 0.4µm 64Mbit, 0.25µm 256Mbit, 0.16um 1Gbit, 0.13µm 2Gbit and 56nm 8Gbit NAND flash memories. He holds 210 patents worldwide including 109 U.S. patents. Especially, with his invention, "multipage cell architecture", presented at Symposium on VLSI Circuits in 1997, he successfully commercialized world's first multi-level cell NAND flash memory in 2001. He has authored numerous technical papers, one of which won the Takuo Sugano Award for Outstanding Paper at ISSCC 2007. He has served on the program committee member of International Solid-State Circuits Conference (ISSCC), Asian Solid-State Circuits Conference (A-SSCC), International Memory Workshop (IMW) and Non-Volatile Memory Technology Symposium (NVMTS). He served as a tutorial speaker at ISSCC 2008, SSD forum organizer at ISSCC 2009, 3D-LSI forum organizer at ISSCC 2010, Ultra-low voltage LSI forum organizer at ISSCC 2011 and Robust VLSI System forum organizer at ISSCC 2012.
[Brief Background]
1991 Bachelor of Engineering in Applied Physics, The University of Tokyo
1993 Master of Engineering in Applied Physics, The University of Tokyo
1993 Researcher, ULSI Research Laboratory, R&D Center, Toshiba
2003 Master of Business Administration (MBA), Stanford University
2006 Doctor of Philosophy in Electrical Engineering, The University of Tokyo
2007 Associate Professor, Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo
2008 Associate Professor, Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo
2012 Professor, Department of Electrical, Electronic, and Communication Engineering, Faculty of Science and Engineering, Chuo University

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