Department of Electrical, Electronic, and Communication Engineering,
Faculty of Science and Engineering, Chuo University
Graduate School of Science and Engineering, Chuo University

TOPICS
2017 2016 2015 2014 2013 2012 2011 2010 2009
2008
2011
Mar14,12 Publications:
  • K. Takeuchi, K. Johguchi, T. Morikawa, K. Yoshioka and T. Shintani, "Temperature Controlling Set Method for Multi-Level Cell Phase Change Memories: x10 Fast Write, 80% Energy Saving" International Symposium on Development of Core Technologies for Green Nanoelectronics, 2012.
  • Feb27,12 Publications:
  • EE Times
  • Feb28,12 Publications:
  • K. Higuchi, K. Miyaji, K. Johguchi and K. Takeuchi, "Endurance Enhancement and High Speed Set/Reset of 50nm Generation HfO2?based Resistive Random Access Memory (ReRAM) Cell by Intelligent Set/Reset Pulse Shape Optimization and Verify Scheme," Japanese Journal of Applied Physics (JJAP), vol. 51, no. 2, pp. 02BD07, February 2012.
  • K. Johguchi, T. Hatanaka and K. Takeuchi, "Through-Silicon-Via (TSV) Design with Clustering Structure and Adaptive TSV Control for 3D Solid-State-Drive Boost Converter System," Japanese Journal of Applied Physics (JJAP), vol. 51, no. 2, pp. 02BE02, February 2012.
  • Jan31,12 Publications:
  • T. Hatanaka, K. Johguchi and K. Takeuchi, " 3D-Integration Method to Compensate Output Voltage Degradation of Boost Converter for Compact Solid-State-Drives," IEEE International Conference on 3D System Integration (3D IC), January 2012.
  • Jan17,12 Publications:
  • S. Tanakamaru, C. Hung and K. Takeuchi, "Highly Reliable Lower Power Solid-State Drives (SSDs) Embedded with and Intelligent NAND Flash Memory Controller with Asymmetric Coding and Stripe Pattern Elimination Algorithm," IEEE J. of Solid-State Circuits, vol. 47, no. 1, pp. 85-96, January 2012.
  • Feb 17,12 Publications:
  • K. Miyaji, T. Suzuki, S. Miyano, K. Takeuchi, "6T SRAM With a Carrier-Injection Scheme to Pinpoint and Repair Fails that Achieves 57% Faster Read and 31% Lower Read Energy," Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC), pp. 232-233, 2012.
  • S. Tanakamaru, Y. Yanagihara and K. Takeuchi, "Over-10x-Extended-Lifetime 76%-Reduced-Error Solid-State Drives (SSDs) with Error-Prediction LDPC Architecture and Error-Recovery Scheme," Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC), pp. 424-425, 2012.
  • Nov5,11 Publications:
  • K. Takeuchi, "Highly reliable Low Power Storage Class Memory & NAND Flash Memory Hybrid Solid-State Drive (SSD)," IEEE Non-Volatile Memory Technology Symposium (NVMTS), November 2011.
  • K. Johguchi, T. Shintani, T. Morikawa, K. Yoshioka and K. Takeuchi, "Temperature Controlling Set Method for Multi-Level Cell Phase Change Memories: x10 Fast Write, 80% Energy Saving," IEEE Non-Volatile Memory Technology Symposium (NVMTS), November 2011.
  • Oct3,11 Publications:
  • S. Tanakamaru and K. Takeuchi, "0.5V Operation VTH Loss Compensated DRAM Word-line Booster Circuit for Ultra-Low Power VLSI Systems," IEEE J. of Solid-State Circuits, vol. 46, no. 10, pp. 2406-2415, October 2011.
  • Sep7,11 Publications:
  • K. Miyaji, S. Tanakamaru, K. Honda, S. Miyano and K. Takeuchi, "Improvement of Read Margin and its Distribution by VTH Mismatch Self-Repair in 6T-SRAM with Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection," IEEE J. of Solid-State Circuits, vol. 46, no. 9, pp. 2180-2188, September 2011.
  • Aug26,11 Presentation: SSDM 2011 (Sep 29-30).
  • X.-Z. Zhang, M. Takahashi, K. Takeuchi, S. Sakai, "First 64kb Ferroelectric-NAND Flash Memory Array with 7.5 V Program, 108 Endurance and Long Data Retention," Extended Abstract of International Conference on Solid-State Devices nad Matelals, pp. 975-976, 2011.
  • Y. Shinozuka, K. Miyaji, K. Takeuchi, "A Zero Additional Process to Standard CMOS, 8F2, Scalable Embedded Flash Memory with Drain-side Assisted Erase Scheme," Extended Abstract of International Conference on Solid-State Devices nad Matelals, pp. 981-982, 2011.
  • K. Johguchi, T. Hatanaka, K. Takeuchi, "Adaptive Through-Silicon-Via Control with Clustering for 3D Solid-State-Drive Boost Converter System," Extended Abstract of International Conference on Solid-State Devices nad Matelals, pp. 1057-1058, 2011.
  • K. Miyaji, C. Hung, K. Takeuchi, "Pushing Scaling Limit Due to Short Channel Effects and Channel Boosting Leakage from 13nm to 8nm with SOI NAND Flash Memory Cells" Extended Abstract of International Conference on Solid-State Devices nad Matelals, pp. 128-129, 2011.
  • K. Higuchi, K. Miyaji, K. Johguchi, K. Takeuchi, "50nm HfO2 ReRAM with 50-Times Endurance Enhancement by Set/Reset Turnback Pulse & Verify Scheme" Extended Abstract of International Conference on Solid-State Devices nad Matelals, pp. 1011-1012, 2011.
  • Jun17,11 Presentation: Sysmposium on VLSI Circuits
  • T. Hatanaka and K. Takeuchi, The University of Tokyo, Japan "4-Times Faster Rising VPASS (10V), 15% Lower Power VPGM (20V), Wide Output Voltage Range Voltage Generator System for 4-Times Faster 3D-integrated Solid-State Drives"
  • May31,11 Publications:
  • Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai and Ken Takeuchi, "1.8V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND," IEEE J. of Solid-State Circuits, vol. 46, no. 6, pp. 1478-1487, June 2011.
  • Mayumi Fukuda, Kazuhide Higuchi and Ken Takeuchi, "Non-volatile RAM and NAND Flash Memory-Integrated Solid-State Drives (SSDs) with Adaptive Codeword ECC for 3.6-Times Acceptable Raw Bit Error Rate Enhancement and 97% Power Reduction," Japanese Journal of Applied Physics (JJAP), vol. 50, no.4, pp. 04DE09, April 2011.
  • May23,11 Presentation: IEEE SSCS Kansai Chapter Technical Seminar
  • K. Johguchi, University of Tokyo, "95%-Lower-BER 43%-Lower-Power intelligent Solid-State Drive (SSD) with Asymmetric Coding and Stripe Pattern Elimination Algorithm"
  • May18,11 Presentation: The Seventh International Nanotechnology Conference on Communication and Cooperation
  • Ken Takeuchi, "Storage Class Memory and Memory System Innovation - International Collaboration for Material, Device, Circuit, Signal Processing and OS Integration"
  • Apr18,11 Presentation: Technical Committee on Integrated Circuits and Devices (ICD), Information and Communication Engineers (IEICE)
  • [Invited Talk] Highly reliable low power SSD --Data modulation signal processing technologies of memory cotroller--
    Ken Takeuchi, Shuhei Tanakamaru, Chinglin Hung (Univ. Tokyo)
  • Design of Program-voltage(20V) Booster and TSV for High Speed and Low Power 3-D Solid State Drive System
    Teruyoshi Hatanaka, Koh Johguchi, Koichi Ishida, Tadashi Yasufuku, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi (Univ. of Tokyo)
  • Suppress of Half Select Disturb in 8T-SRAM by Local Injected Electron Asymmetric Pass Gate Transistor
    Kousuke Miyaji, Kentaro Honda, Shuhei Tanakamaru (Univ. of Tokyo), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo)
  • Apr10,11 Publications:
  • Koh Johguchi, Teruyoshi Hatanaka, Koichi Ishida, Tadashi Yasufuku, Makoto Takamiya, Takayasu Sakurai and Ken Takeuchi, “Through-Silicon-Via (TSV) design for a 3D-Solid-State-Drive (SSD) System with Boost Converter in a Package,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 1, no. 2, pp. 269-277, February 2010.
  • Shuhei Tanakamaru, Mayumi Fukuda, Kazuhide Higuchi, Atsushi Esumi, Mitsuyoshi Ito, Kai Li and Ken Takeuchi, “Post-manufacturing, 17-times Acceptable Raw Bit Error Rate Enhancement, Dynamic Codeword Transition ECC Scheme for Highly Reliable Solid-State Drives, SSDs,” Solid-State Electronics, vol. 58, no. 1, pp. 2-10, April 2011.
  • Kousuke Miyaji, Shinji Noda, Teruyoshi Hatanaka, Mitsue Takahashi, Shigeki Sakai and Ken Takeuchi, “A 1.0V Power Supply, 9.5GByte/sec Write Speed, Single-Cell Self-Boost Program Scheme for Ferroelectric NAND Flash SSD,” Solid-State Electronics, vol. 58, no. 1, pp. 34-41, April 2011.
  • Teruyoshi Hatanaka, Mitsue Takahashi, Shigeki Sakai and Ken Takeuchi, “Improvement of Read Disturb, Program Disturb and Data Retention by Memory Cell VTH Optimization of Ferroelectric (Fe)-NAND Flash Memories for Highly Reliable and Low Power Enterprise Solid-State Drives (SSDs),” IEICE Transactions on Electronics, vol. E94-C, no. 4, pp. 539-547, April 2011.
  • Apr02,11 Publication:
    Interview article on the Monthly Magazine "ChiChi" (in Japanese).

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