Department of Electrical, Electronic, and Communication Engineering,
Faculty of Science and Engineering, Chuo University
Graduate School of Science and Engineering, Chuo University

TOPICS
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2008
2012
Feb9,13 Publications:
  • Shuhei Tanakamaru, Masafumi Doi and Ken Takeuchi,"Unified Solid-State Storage Architecture with NAND Flash Memory and ReRAM that Tolerates 32X Higher BER for Big-Data Applications," IEEE International Solid-State Circuits Conference (ISSCC), pp. 226-227, 19 February 2013.
  • Jan22,13 Publications:
  • Shuhei Tanakamaru, Yuki Yanagihara and Ken Takeuchi,"Highly Reliable Solid-State Drives (SSDs) with Error-Prediction LDPC (EP-LDPC) Architecture and Error-Recovery Scheme," 18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013) University LSI Design Contest, pp. 83-84, January 2013.
  • Chao Sun, Hiroki Fujii, Kousuke Miyaji, Koh Johguchi, Kazuhide Higuchi and Ken Takeuchi,"Highly Reliable Solid-State Drives (SSDs) with Error-Prediction LDPC (EP-LDPC) Architecture and Error-Recovery Scheme," 18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013) University LSI Design Contest, pp. 81-82, January 2013.
  • Nov29,12 Publications:
  • K. Takeuchi,"Hybrid Memory Architecture of PCM and NAND flash memories for Enterprise Storage ," Phase Change Oriented Science (PCOS), November 2012.
  • K. Johguchi, K. Yoshioka and K. Takeuchi, "High Density NAND Phase Change Memory with Block-Erase Architecture and Investigations for Write and Disturb Requirements,"Phase Change Oriented Science (PCOS), November 2012.
  • Nov18,12 Presentation:
  • K. Takeuchi, "Highly Reliable Signal Processing Technologies for Dependable Solid-State Drives (SSDs)," The 18th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), p. 21, November 2012.<Invited>
  • Nov15,12 Presentation:
  • K. Takeuchi, "Signal Processing and Data Management Technologies for NAND&ReRAM Hybrid SSD ," New Non-Volatile Memory Workshop 2012, November 2012.
  • Non13,12 Publications:
  • T. Hatanaka and K. Takeuchi, "VSET/RESET and VPGM Generator without Boosting Dead Time for 3D-ReRAM and NAND flash Hybrid Solid-State Drives," IEEE Asian Solid-State Circuits Conference (A-SSCC), November 2012.
  • K. Miyaji, K. Johguchi, K. Higuchi and K. Takeuchi, "An Integrated Variable Positive/Negative Temperature Coefficient Read Reference Generator for MLC PCM/NAND Hybrid 3D SSD,"IEEE Asian Solid-State Circuits Conference (A-SSCC), November 2012.
  • Nov7,12 Presentation:
  • K. Takeuchi,"Variability and Failure Recovery of SRAM and Flash Memory," IEEE/ACM Workshop on Variability Modeling and Characterization (VMC), November 2012.
  • Oct31,12 Publications:
  • K. Takeuchi,"Sophisticated Error Correction and Data Management Technologies for Storage Class Memory & NAND Flash Memory Hybrid Solid-State Drives (SSD)," NVMTS, October 2012.
  • C. Sun, K. Miyaji, K. Johguchi and K. Takeuchi, "x8 High Write-Throughput, 84% Write-Energy Saving, x6.5 Extended Lifetime Hybrid ReRAM/MLC NAND SSD with Cold Data Eviction Algorithm, "NVMTS, October 2012.
  • Sep24,12 Publications:
  • Tomoko Ogura Iwasaki, Sheyang Ning and Ken Takeuchi, "Bipolar Read in ReRAM for 3x Write Speed and 5x Faster Read with Disturb Immunity," International Conference on Solid State Devices and Materials (SSDM), September 2012.
  • Jul28,12 Publications:
  • K. Miyaji, Y. Shinozuka, S. Miyano and K. Takeuchi, "Near Threshold Voltage Word-line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM," IEEE Transactions on Circuits and Systems I, vol. 59, no. 8, pp. 1635-1643, August 2012
  • Jun23,12 Publications:
  • T. Hatanaka and K. Takeuchi, "“NAND Controller System with Channel Number Detection and Feedback for Power-Efficient High-Speed 3D-SSD," IEEE J. of Solid-State Circuits, vol. 47, no. 6, pp. 1460-1468, June 2012.
  • May20,12 Publications:
  • K. Takeuchi, T. Hatanaka and S. Tanakamaru, "Highly Reliable, High Speed and Low Power NAND Flash Memory-Based Solid State Drives (SSDs)," IEICE Electronics Express (ELEX), vol. 9, no. 8, pp. 779-794, 2012.
  • May20,12 Publications:
  • K. Miyaji, Y. Shinozuka and K. Takeuchi, "Zero Additional Process, Local Charge Trap, Embedded Flash Memory with Drain-side Assisted Erase Scheme Using Minimum Channel Length/Width Standard CMOS Single Transistor Cell," Japanese Journal of Applied Physics (JJAP), vol. 51, no. 4, pp. 04DD02, April 2012.
  • K. Miyaji, C. Hung and K. Takeuchi, "Scaling Trends and Tradeoffs between Short Channel Effect and Channel Boosting Characteristics in sub-20nm Bulk/SOI NAND Flash Memory," Japanese Journal of Applied Physics (JJAP), vol. 51, no. 4, pp. 04DD12, April 2012.
  • K. Miyaji, R. Yajima, T. Hatanaka, M. Takahashi, S. Sakai and K. Takeuchi, "Initialize & and Weak-Program Erasing Scheme and Single-Pulse Programming Scheme for High-Performance and High-Reliability Ferroelectric NAND Flash Solid-State Drive," IEICE Transactions on Electronics, E95-C, no. 4, pp. 609-616, April 2012.
  • K. Miyaji, K. Honda, S. Tanakamaru, S. Miyano and K. Takeuchi, "Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor," IEICE Transactions on Electronics, E95-C, no. 4, pp. 564-571, April 2012.
  • Apr2,12 Publications:
  • H. Fujii, K. Miyaji, K. Johguchi, K. Higuchi, C. Sun and K. Takeuchi, "Performance Increase, x6.9 Endurance Enhancement, 93% Energy Reduction of 3D TSV-Integrated Hybrid ReRAM/MLC NAND SSDs by Data Fragmentation Suppression"

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